Second Technical Symposium on Reconfigurable Computing with FPGAs - Abstracts

C Programming for Reconfigurable HPC - Case Study Lattice Gas

David Shand, Nallatech

David Shand, of Nallatech, has been working with their latest C based design environment (DIMEtalk and DIME-C) to assess the practical steps involved in generating an FPGA based processing system.

The presentation takes us through the implementation of a simple fluid dynamic model in order to show the development process, as well as what can be achieved.

Implementing HPC Algorithms in FPGA accelerated systems

Steve Chappell, Director of Applications Engineering, Celoxica

There are compelling reasons to consider "FPGA Accelerators" in HPC system infrastructure. They can be a natural choice for accelerating integer-based, wide datapath and massively parallel computation. Moreover, the current generation of devices can enable fast parallel floating-point calculations in many applications.

Managing the complexity of FPGA hardware design in a predominantly software driven application sector is a particular challenge for the development of reconfigurable computing applications. We will describe a software-compiled system design methodology using C-synthesis and hardware-software partitioning tools that overcomes these challenges. Unlike traditional hardware design or block based design entry, these technologies provide a practical and familiar design flow for HPC application developers to explore the acceleration of software systems.

Using FPGAs in Supercomputers: Breaking with Reconfigurable Computing

Stefan Mohl, co-founder, Mitrionics

The current practices in the field of Reconfigurable Computing are almost exclusively rooted in traditional hardware development practices. The tools used, the development techniques employed and the problem domains addressed with FPGAs are currently locked squarely in the realm of hardware design.

Current supercomputing systems incorporate large FPGAs, fully integrated as computational units. We will argue that the methodologies for circuit design are not suitable in this environment.

Three paths have emerged to remedy this situation. One is the bottom-up approach, where circuit design methods are simplified and abstracted. The hope is to allow circuit design with methods that are similar to software programming. A second approach is top-down, where software in the more traditional sense is run in a hand-crafted circuit, i.e. a processor. To take advantage of FPGA re-configurability, such a processor must be massively parallel and adapted for each application through an automated process. Finally, a third approach is to hand-craft circuits for specific algorithms that can then run in an FPGA as accelerated library functions.

The solution adopted by Mitrionics is the top-down approach. A system is presented, on top of which FPGAs can be programmed at the actual software level. The Mitrion platform does not permit any circuits to be designed, it only permits running an application in the Mitrion Virtual Processor. On the other hand, we hope to achieve a level of abstraction that is equal or higher than traditional parallel programming methods for FORTRAN or C. When programming with the Mitrion platform, focus is shifted from implementation to description. The Mitrion platform strives for a level of abstraction where code is written for readability, clarity and maintainability. In contrast, circuit design methods focus on the exact positioning of data in the silicon during each clock-cycle. By adopting the top-down approach, many of the traditional problem domains addressed by FPGA systems are abandoned. On the other hand, many new problem domains are opened up.

The principles behind this system and a taste of the intrinsically parallel programming language Mitrion-C will be presented.

FHPCA - a general purpose 64-FPGA supercomputer

Rob Baxter, EPCC

The FPGA High Performance Computing Alliance (FHPCA) is focused on the development of computing solutions using FPGAs to deliver new levels of performance. This will be achieved through the implementation of a large scale demonstrator or "Supercomputer" and supported by a structured programme of knowledge diffusion designed to raise industry awareness, interest and create commercial advantage.

The alliance partners are: Algotronix, Alpha Data Parallel Systems, EPCC, the Institute for System Level Integration, Nallatech, Scottish Enterprise and Xilinx. This talk will offer some background on the Alliance and a review of the current status of the supercomputer project. It will cover the current high level system design, summarise our thinking on a vendor-neutral hardware-abstraction programming model and touch upon the ongoing porting programme for commercial demonstration codes.

This symposium was brought together by the University of Manchester and in conjunction with its sponsors: